73 research outputs found

    An Alternative Realization of Droop Control and Virtual Impedance for Paralleled Converters in DC Microgrid

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    Constant Power Load Instability Mitigation in DC Shipboard Power Systems Using Negative Series Virtual Inductor Method

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    Comparative Admittance-based Analysis for Different Droop Control Approaches in DC Microgrids

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    Computation of the maximal invariant set of discrete-time linear systems subject to a class of non-convex constraints

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    We consider the problem of computing the maximal invariant set of discrete-time linear systems subject to a class of non-convex constraints that admit quadratic relaxations. These non-convex constraints include semialgebraic sets and other smooth constraints with Lipschitz gradient. With these quadratic relaxations, a sufficient condition for set invariance is derived and it can be formulated as a set of linear matrix inequalities. Based on the sufficient condition, a new algorithm is presented with finite-time convergence to the actual maximal invariant set under mild assumptions. This algorithm can be also extended to switched linear systems and some special nonlinear systems. The performance of this algorithm is demonstrated on several numerical examples.Comment: Accepted in Automatic

    A Heuristic Scheduler for Port-Constrained Floating-Point Pipelines

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    We describe a heuristic scheduling approach for optimizing floating-point pipelines subject to input port constraints. The objective of our technique is to maximize functional unit reuse while minimizing the following performance metrics in the generated circuit: (1) maximum multiplexer fanin, (2) datapath fanout, (3) number of multiplexers, and (4) number of registers. For a set of systems biology markup language (SBML) benchmark expressions, we compare the resource usages given by our method to those given by a branch-and-bound enumeration of all valid schedules. Compared with the enumeration results, our heuristic requires on average 33.4% less multiplexer bits and 32.9% less register bits than the worse case, while only requiring 14% more multiplexer bits and 4.5% more register bits than the optimal case. We also compare our results against those given by the state-of-art high-level synthesis tool Xilinx AutoESL. For the most complex of our benchmark expressions, our synthesis technique requires 20% less FPGA slices than AutoESL

    A Synchronous-Reference-Frame I-V Droop Control Method for Parallel-Connected Inverters

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